The present invention relates to the assembly and packaging of semiconductor chips. More particularly, the present invention relates to assembly and packaging of wire-bonded dies in semiconductor chips. Even more particularly, the present invention relates to reducing shear stress in the dies of semiconductor chips.
Currently, the semiconductor industry is demanding better die attach, better packaging, better wire-bonding, and the like, to improve product reliability. Each die is generally attached into a die attach area of a semiconductor package using a eutectic material layer, such as a gold-silicon (Auxe2x80x94Si) eutectic layer and a silver-silicon (Agxe2x80x94Si), or an organic die attach material, such as an epoxy or a polyimide. Distal ends of a wire are generally respectively bonded to a die and to a lead. A chip is generally secured well into the package; and the die attachment area may provide electric coupling between the chip and the remainder of the lead system. A major requirement for the die attachment area is that it be extremely flat to intimately retain the chip in the package.
With respect to die attachment, the basic objective is to provide the best adhesion between the chip and the package as is possible and to provide the best electrically and/or thermally conducting path or even the best insulating material therebetween, depending on the specific chip application. As such, the die attachment should be strong to prevent delamination during subsequent processing steps or during use. The most widely used die attach materials include gold-filled (Au) and silver-filled (Ag) polyimides and epoxies for electrical and thermal conduction. For insulation purposes, silica-loaded polymers may be used as a die attach material. Unfortunately, both insulator-filled and conductor-filled related art die attach materials tend to delaminate and crack due to their inherent internal stresses after curing. Further, most molding compounds tend to flex around the die during temperature cycling, also inducing cracking or propagating pre-existing cracks.
The related art has attempted to address these issues by providing lower stress molding compounds and lower stress die attach epoxies. However, the use of lower stress molding compounds would require requalification of many existing products. Such product conversions are both difficult and exorbitant. In addition, using a lower stress molding compound requires a decreased loading of silica (SiO2) particles which, then, compromises thermal performance. Similarly, using a lower stress die attach epoxy requires a decreased loading of Au or Ag particles, compromising not only thermal performance but also electrical performance.
Another related art approach has been to use a very low epoxy fillet height in the range of less than 33.33% (i.e.,  less than 5 mils fillet height for a 15-mil thick die) for reducing any thermally-induced stress only at the die/encapsulant interface, wherein the encapsulant specifically comprises a glob-top material. Typically, a glob-top encapsulant is known to have inherent weaknesses at the die/glob-top interface, because it is dispensed from a dispenser under ambient conditions over and onto the die""s upper surface. As such, the glob-top encapsulant tends to be riddled with voids, compromising adhesion, and therefore, contributing to delamination. However, this related art approach does not address the problem of shear stress in the fillet, in the cracking of a thicker die, nor between the metal circuitry and the bulk silicon on the die. Likewise, these related art techniques do not address problems related to packaging materials other than those associated with the glob-top variety. Therefore, a long-felt need is seen to exist for a method and an apparatus for controlling the die attachment process in order to prevent cracking as well as delamination in a semiconductor chip package under many processing and use conditions.
Accordingly, the present invention provides a method and an apparatus for preventing cracking and delamination in a semiconductor chip package, especially a xe2x80x9cplasticxe2x80x9d package, such as a plastic quad flat package (PQFP), a thin quad flat package (TQFP), a plastic leadless chip carrier (PLCC) package, a small outline integrated circuit (SOIC) package, although less problematic, some undesirable shear stress may still exist), and any other standard or nonstandard plastic package. Particularly, a ball grid array (BGA) package with an over-molded compound (or xe2x80x9cmolding compoundxe2x80x9d), which also experiences cracking and delamination during thermal cycling, thermal shock, or normal operation.
The present invention solves these plastic packaging problems by controlling the die attach fillet height, thereby reducing shear stress in the die itself. The molding compound, such as is used with a BGA, may be applied by dispensing it through gate in a transfer mold (e.g., RTM: resin transfer molding). After filling the mold with the molding compound, heat and pressure may be applied for curing, densifying, and devoiding the molding compound. This technique, when used in the present method for controlling fillet height, results in a non-delaminating semiconductor package, especially for a BGA.
By example only, the present invention empirical data corresponds to various fillet heights that are proportional to various die thicknesses in a range of approximately 4 mils to 30 mils contained in a BGA package under experimental conditions, such as thermal cycling and thermal shock. By using a fillet height in a preferred range of greater than approximately 33% to approximately 75% of the die thickness, the present invention circumvents both (1) the related art problem of coefficient of thermal expansion (CTE) mismatch among the elements within a packaged device, which would otherwise occur in the related art fillet height range of  less than 33% of the die thickness, thereby leading to voids in the die attach material, cracking thereof, and poor thermal conductivity; and (2) the related art problem of high shear stress-induced failures, such as shear stress-induced cracking in the die attach material as well as the die itself, which would otherwise occur in the related art fillet height range of  greater than 75% of the die thickness. Surprisingly, the present invention experimental reliability data demonstrates that a nominal fillet height of approximately 50% of the die thickness induces the lowest shear stress in a thicker silicon die (e.g., in a range of approximately 8 mils to approximately 14 mils, preferably in a range of approximately 10 mils to approximately 14 mils). Also surprisingly, a thinner die having a thickness in a range of less than 8 mils, actually imparts adverse results in contravention to the semiconductor packaging industry""s belief. A die attach pick-and-place machine, such as an ESEC 2007(trademark), may be used in the present invention. More specifically, the present invention provides a method and an apparatus controlling the die attach epoxy height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself.
Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, the present invention also has the advantage of compromising neither thermal performance nor electrical performance. Also, by controlling the fillet height by regulating the amount of die attach material to be applied, less die attach material is consumed in the packaging process. As such, the present invention method and apparatus prevent cracking and delamination in a semiconductor chip package, especially a ball grid array (BGA) package, during thermal cycling, thermal shock, and normal use, thereby resulting in a more robust package.